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ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. vii
List of Figures
PrimeCell AHB SRAM/NOR Memory Controller
(PL241) Technical Reference Manual
Key to timing diagram conventions ............................................................................. xii
Figure 1-1 AHB MC (PL241) configuration ................................................................................. 1-2
Figure 2-1 AHB MC (PL241) configuration ................................................................................. 2-2
Figure 2-2 AHB MC (PL241) clock domains ............................................................................... 2-3
Figure 2-3 SMC block diagram ................................................................................................... 2-4
Figure 2-4 SMC SRAM pad interface external connections ....................................................... 2-6
Figure 2-5 Big-endian implementation ...................................................................................... 2-10
Figure 2-6 AHBC memory map ................................................................................................ 2-11
Figure 2-7 Request to enter low-power mode .......................................................................... 2-13
Figure 2-8 AHB domain denying a low-power request ............................................................. 2-13
Figure 2-9 Accepting requests .................................................................................................. 2-14
Figure 2-10 SMC aclk domain FSM ........................................................................................... 2-15
Figure 2-11 Chip configuration registers .................................................................................... 2-23
Figure 2-12 Device pin mechanism ............................................................................................ 2-25
Figure 2-13 Software mechanism ............................................................................................... 2-26
Figure 2-14 Asynchronous read ................................................................................................. 2-29
Figure 2-15 Asynchronous read in multiplexed-mode ................................................................ 2-29
Figure 2-16 Asynchronous write ................................................................................................. 2-30
Figure 2-17 Asynchronous write in multiplexed-mode ................................................................ 2-31
Figure 2-18 Page read ................................................................................................................ 2-32
Figure 2-19 Synchronous burst read .......................................................................................... 2-33
- PrimeCell 1
- AHB SRAM/NOR 1
- Memory Controller (PL241) 1
- Technical Reference Manual 2
- Contents 3
- List of Tables 5
- List of Figures 7
- • About this manual on page x 9
- • Feedback on page xiv 9
- About this manual 10
- Preface 11
- Feedback 14
- Chapter 1 15
- Introduction 15
- 1.1 About the AHB MC 16
- 1.2 Supported devices 19
- Chapter 2 21
- Functional Overview 21
- 2.1 Functional description 22
- Figure 2-3 SMC block diagram 24
- 2.3 Functional operation 27
- Figure 2-6 AHBC memory map 31
- Figure 2-9 Accepting requests 34
- 2.4 SMC functional operation 35
- Standard SRAM access 40
- Memory address shifting 40
- Memory burst alignment 40
- Memory burst length 41
- Booting using the SRAM 41
- = 7, and t 49
- &(2( 53
- Programming t 58
- Chapter 3 61
- Programmer’s Model 61
- Figure 3-1 SMC register map 62
- 3.2 Register summary 63
- Type Reset value Description 65
- 3.3 Register descriptions 66
- LQWBHQDEOH 68
- 5HVHUYHG 68
- ORZBSRZHUBUHT 68
- 8QGHILQHG 68
- LQWBGLVDEOH 69
- ORZBSRZHUBH[LW 69
- 78
- VPFBXVHUBVWDWXV8QGHILQHG 78
- 0xFE0-0xFEC 79
- Bits Name Function 80
- 0xFF0-0FFC 82
- 0xB105F00D 82
- Chapter 4 85
- Programmer’s Model for Test 85
- Chapter 5 89
- Device Driver Requirements 89
- 5.1 Memory initialization 90
- Appendix A 95
- A.1 About the signals list 96
- A.2 Clocks and resets 97
- A.3 AHB signals 98
- A.5 SMC miscellaneous signals 100
- A.6 Low-power interface 101
- A.7 Configuration signal 102
- A.8 Scan chains 103
- Signal Descriptions 104
- Glossary 105
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